Maurer computers for pipelined instruction processing

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Maurer computers for pipelined instruction processing

Maurer computers for pipelined instruction processing† J. A. BERGSTRA‡ and C. A. MIDDELBURG§ ‡Programming Research Group, University of Amsterdam, P.O. Box 41882, 1009 DB Amsterdam, the Netherlands and Department of Philosophy, Utrecht University, P.O. Box 80126, 3508 TC Utrecht, the Netherlands Email: [email protected] §Programming Research Group, University of Amsterdam, P.O. Box 41882, 100...

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Maurer Computers with Single-Thread Control

We present the development of a theory of stored threads and their execution. The work builds upon Maurer’s theory of computer instructions and the thread algebra of Bergstra et al. The theory being developed is primarily relevant to the design of new processor architectures. We also relate Maurer’s model for computers with Turing machines, and stored threads with programs as considered in the ...

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Pipelined Decomposable BSP Computers

The class of weak parallel machines is interesting, because it contains some realistic parallel machine models, especially suitable for pipelined computations. We prove that a modification of the bulk synchronous parallel (BSP) machine model, called decomposable BSP (dBSP), belongs to the class of weak parallel machines if restricted properly. We will also correct some earlier results about pip...

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On Transformations of Load-Store Maurer Instruction Set Architectures

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ژورنال

عنوان ژورنال: Mathematical Structures in Computer Science

سال: 2007

ISSN: 0960-1295,1469-8072

DOI: 10.1017/s0960129507006548